MARCO GSRC Calibrating Achievable Design Theme

GTX: The GSRC Technology Extrapolation System

text Last update: August 18, 2003


We suggest that first-time visitors first read the basic information on the GTX framework and then follow the steps in "Before you run GTX ..." and the examples in the user manual to learn the various possibilities of GTX.

General Users Model developers GTX developers

GTX can only become the repository of first choice for technology extrapolation if enough ``experts'' are willing to contribute their models to GTX. Current contributions are acknowledged in the contributions page. If you would like to contribute models and/or studies to GTX, please contact (how to contribute).

We would very much appreciate any feedback you may have on the GTX architecture, rules, or web site.

Research activity related to GTX has been generously supported by Mentor Graphics Corporation under a 1998-1999 UC MICRO project, and by Synopsys, Inc. under a 1999-2000 UC MICRO project. GTX also draws on the 1997-1998 work on CONCORD by Kahng, Johann, Vidhani and Wang at UCLA.


"Calibrating Achievable Design" is one of four themes in the MARCO GSRC. Supporting this theme are three initiatives, "Technology Extrapolation", "CAD-IP Reuse", and "Metrics".

Technology extrapolation -- i.e., the calibration and prediction of achievable design in future technology generations -- drives the evolution of VLSI system architectures, design methodologies, and design tools. It informs our picture of where and when future hard design issues must arise -- e.g., power/current management, global synchronization, high-speed global signaling, layout on-the-fly -- and how far particular methodologies (i.e., restrictions to the available solution space) will take us in maintaining productivity with acceptable QOR penalty. Its scope ranges from device/interconnect modeling to system architecture models and metrics; from top-level wirelength distributions to implications of SOI on delay analysis accuracy. Via roadmapping efforts such as the International Technology Roadmap for Semiconductors (ITRS), technology extrapolation also influences levels of investment in various areas of academic research, private-sector entrepreneurial activity, and other facets of VLSI design automation.

GTX, the MARCO GSRC Technology Extrapolation system, seeks to provide a robust, portable framework for the interactive specification and comparison of alternative modeling choices, e.g., for predicting system cycle time, die size, or power dissipation. Unlike previous "hard-coded" systems, GTX adopts a paradigm wherein parameters and rules allow users to flexibly capture attributes and relationships germane to VLSI technology and design. Serialized user-defined rules can be composed in numerous ways to define rule chains, which are then executed by a derivation engine to perform studies. Supporting grammars, parameter naming conventions, extension mechanisms, etc. enable GTX to incorporate -- and serve as a repository for -- literally unlimited forms of domain knowledge.

GTX intends to meld the rich heritage of VLSI technology extrapolation originated by Bakoglu/Meindl (SUSPENS), Sai-Halasz, GENESYS, RIPE, BACPAC, etc. with the paradigm of flexibility established in the AI constraint programming and design support literatures (DesignSheet, UniCalc/NeMo, etc.), along with improved optimization and visualization capabilities. Our current objectives include the following.