My name is Wei-Ting (Jonas) Chan. I am a Ph.D. candidate in UCSD VLSI/CAD laboratory, working under the supervision of Professor Andrew B. Kahng. My research interests including physical design in advanced nodes and non-conventional VLSI design. Before my Ph.D. study, I was an RTL designer and familiar with tapeout flow. I had several tapeout experiences for productized CMOS imaging SoCs from 2006 to 2010.
Here is my CV.
About my photo.