Last Modified: October 11, 2006
Bao Liu
Post-Doctoral Researcher

University of California, San Diego
CSE and ECE Departments
9500 Gilman Drive
La Jolla, CA 92093-0114

Work Phone: (858) 822-5003
Fax: (858) 534-7029
Email: bliu@cs.ucsd.edu
Office: AP&M 3819


Home Page of Bao Liu

Areas of Interest

VLSI physical design automation: timing analysis and delay calculation, signal integrity analysis, yield and variation aware optimization, timing-driven interconnect synthesis.

Biographical Sketch

Dr. Liu received his Ph.D. degree in Computer Science and Engineering from UCSD in 2003, and his B.S. and M.S. degrees in Electrical Engineering from Fudan University, China in 1993 and 1996, respectively. He worked with China IC Design Center in 1996-1998, Cadence Design Systems, Inc. in 1999, Conexant Systems, Inc. in 2000, Incentia Design Systems, Inc. in 2002-2004, and Cadence Design Systems, Inc. in 2004, respectively. He is currently a post-doctoral researcher with Professor Andrew Kahng in the Computer Science and Engineering Department, and a lecturer in the Electrical and Computer Engineering Department at UCSD.


Dr. Liu's current research focuses on VLSI design performance verification, signal integrity analysis, and corresponding optimization techniques.

Selected Publications

  1. A. B. Kahng, B. Liu, and I. Mandoiu, "Non-Tree Routing for Reliability and Yield Improvement", (.ps), (.pdf), IEEE Trans. on Computer-Aided Design, 23(1), 2004, pp. 148-156.  
  2. C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu, and A. Zelikovsky, "On the Skew-Bounded Minimum-Buffer Routing Tree Problem", (.ps), (.pdf), IEEE Trans. on Computer-Aided Design, 22(7), 2003, pp. 937-945.
  3. C.-K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, "Toward Better Wireload Models in the Presence of Obstacles", (.ps), (.pdf), IEEE Trans. on VLSI Systems, 10(2), 2002, pp. 177-188.
  4. A. B. Kahng and B. Liu, "Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization", (.ps), (.pdf), (.ppt), IEEE Comp. Soc. Annual Symp. on VLSI, 2003, pp. 183-188.

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